Qual o comportamento do circuito descrito pelo código abaixo, escrito em Very High Speed Integrated Circuit Hardware Description Language (VHDL)?

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY circuito IS
GENERIC (size: INTEGER := 3);
PORT (Clock, Clear, Load: IN std_logic;
X: IN std_logic_vector(size DOWNTO 0);
Y: OUT std_logic_vector(size DOWNTO 0));

END;

ARCHITECTURE Behavior OF circuito IS
BEGIN
PROCESS (Clock, Clear)
BEGIN
IF Clear = '1' THEN
Y <= (OTHERS => '0');
ELSIF Clock'EVENT AND Clock = '1' THEN
IF Load = '1' THEN
Y <= X;
END IF;
END IF;
END PROCESS;
END;

Assinale a alternativa que responde CORRETAMENTE à questão acima.